Journal Conference Patents
Journal Papers 共 43 篇
(1) Jen-Chieh Liu, Yo-Hao Tu, Kuo-Hsing Cheng, and Chi-Yang Chang,“Low supply voltage and multiphase all-digital crystal-less clock generator,”IET Circuits, Devices & Syst.
, vol. 12 , no. 6 , pp. 720-725 ,
Aug. 2018 (SCI)
(2) Yo-Hao Tu, Kuo-Hsing Cheng, Man-Ju Lee, and Jen-Chieh Liu,“A power-saving adaptive equalizer with a digital-controlled self-slope detection,”IEEE Trans. Circuits Syst. I, Reg. Papers
, vol. 65 , no. 7 , pp. 2097–2108 ,
Jul. 2018 (EI,SCI)
(3) Yo-Hao Tu, Jen-Chieh Liu, Kuo-Hsing Cheng, and Chih-Hsun Hsu,“A 0.5-V all-digital clock-deskew buffer with I/Q phase outputs,”Analog Integrated Circuits and Signal Processing
, vol. 93 , no. 1 , pp. 157–167 ,
Oct. 2017 (SCI)
(4) Chih-Wei Tsai, Yu-Lung Lo, Chia-Chen Chang, Han-Ying Liu, Wei-Bin Yang, and Kuo-Hsing Cheng,“All-digital duty-cycle corrector with synchronous and high accuracy output for double date rate synchronous dynamic random-access memory application,”Japanese J. of Appl. Physics
, vol. 56 , no. 4S , pp. 04CF02-1 - 04CF02-6 ,
Jan. 2017
(5) Yo-Hao Tu, Jen-Chieh Liu, and Kuo-Hsing Cheng,“Proportional static-phase-error reduction for frequency-multiplier-based delay-locked-loop architecture,”IEICE Trans. on Electronics
, vol. E99-C , no. 6 , pp. 655-658 ,
Jan. 2016 (SCI)
(6) Yo-Hao Tu, Jen-Chieh Liu, Kuo-Hsing Cheng, Hong-Yi Huang, and Chang-Chien Hu,“A 0.6-V 1.6-GHz 8-phase all digital PLL using multi-phase based TDC,”IEICE Electronic Express
, vol. 13 , no. 2 , pp. 1-12 ,
Jan. 2016 (SCI)
(7) Kuo-Hsing Cheng, Cheng-Liang Hung, Alex Gong C.-S., Jen-Chieh Liu, Bo-Qian Jiang and Shi-Yang Sun,“A 0.9- to 8-GHz VCO with a differential active inductor for multistandard wireline SerDes,”IEEE Trans. Circuits Syst. II, Express Briefs
, vol. 61 , no. 8 , pp. 559-563 ,
Aug. 2014 (EI,SCI)
(8) Kuo-Hsing Cheng, Jen-Chieh Liu, and Hong-Yi Huang,“A 0.6-V 800-MHz All-Digital Phase-Locked Loop with a Digital Supply Regulator,”IEEE Trans. Circuits Syst. II, Express Briefs
, vol. 59 , no. 12 , pp. 888 - 892 ,
Dec. 2012 (EI,SCI)
(9) Kuo-Hsing Cheng, Kai-Wei Hong, Chi-Fa Hsu, and Bo-Qian Jiang ,“An All-Digital Clock Synchronization Buffer With One Cycle Dynamic Synchronizing,”IEEE Trans. Very Large Scale Integr. Syst.
, vol. 20 , no. 10 , pp. 1818-1827 ,
Oct. 2012 (EI,SCI)
(10) Shyh-Shyuan Sheu, Kuo-Hsing Cheng, Yu-Sheng Chen, Pang-Shiu Chen, Ming-Jinn Tsai, and Yu-Lung Lo,“A 50ns Verify Speed in Resistive random access memory by using a Write Resistance Tracking Circuit,”IEICE TRANSACTIONS ON ELECTRONICS
, vol. E95-C , no. 6 , pp. 1128-1131 ,
Jun. 2012 (SCI)
(11) Jen-Chieh Liu, Hong-Yi Huang, and Kuo-Hsing Cheng,“A 0.3 Volt All Digital Crystal-less Clock Generator,”ICL Technical Journal
, vol. 143 , no. 2 , pp. 126-133 ,
Feb. 2012
(12) Kuo-Hsing Cheng, Jen-Chieh Liu, and Hong-Yi Huang,“A 6-GHz Built-in Jitter Measurement Circuit Using Multiphase Sampler,”IEEE Trans. Circuits Syst. II, Express Briefs
, vol. 58 , no. 8 , pp. 492 ,
Aug. 2011 (EI,SCI)
(13) Kuo-Hsing Cheng, Kai-Wei Hong, Chi-Hsiang Chen, and Jen-Chieh Liu,“A High Precision Fast Locking Arbitrary Duty Cycle Clock Synchronization Circuit,”IEEE Trans. Very Large Scale Integr. Syst.
, vol. 19 , no. 7 , pp. 1218-1228 ,
Jul. 2011 (EI,SCI)
(14) Kuo-Hsing Cheng, Cheng-Liang Hung, and Chih-Hsien Chang,“A 0.77 ps RMS Jitter 6-GHz Spread-Spectrum Clock Generator Using a Compensated Phase-Rotating Technique,”IEEE J. Solid-State Circuits
, vol. 46 , no. 5 , pp. 1198-1213 ,
May 2011 (EI,SCI)
(15) Kuo-Hsing Cheng, Yu-Chang Tsai, Yu-Lung Lo, and Jing-Shiuan Huang,“A 0.5-V 0.4–2.24-GHz Inductorless Phase-Locked Loop in a System-on-Chip ,”IEEE Trans. Circuits Syst. I, Reg. Papers
, vol. 58 , no. 5 , pp. 849 ,
May 2011 (EI,SCI)
(16) Shyh-Shyuan Sheu and Kuo-Hsing Cheng,“Fast-Write Resistive RAM (RRAM) for Embedded Applications,”IEEE Design & Test of Computers
, vol. 28 , pp. 64-71 ,
Feb. 2011
(17) Kuo-Hsing Cheng, Kai-Wei Hong, Yu-Lung Lo, Chen-Lung Wu and Chien-Hsien Lee,“Dynamic frequency tracking and phase error compensation clock de-skew buffer,”IEE Electronics Letters
, vol. 46 , no. 25 , pp. 1653-1655 ,
Dec. 2010 (EI,SCI)
(18) Kuo-Hsing Cheng, Jen-Chieh Liu, Chih-Yu Chang, Shu-Yu Jiang, and Kai-Wei Hong,“Built-in Jitter Measurement Circuit with Calibration Techniques for a 3 GHz Clock Generator,”IEEE Trans. Very Large Scale Integr. Syst.
, pp. 1325-1335 ,
Jun. 2010 (EI,SCI)
(19) Kuo-Hsing Cheng, Yu-Chang Tsai, Yen-Hsueh Wu, and Ying-Fu Lin,“A 5Gb/s Inductorless CMOS Adaptive Equalizer for PCI Express Generation II Applications,”IEEE Trans. Circuits Syst. II, Express Briefs
, pp. 324-328 ,
May 2010 (EI,SCI)
(20) Kuo-Hsing Cheng, Shu-Yu Jiang, and Pei-Yi Jian,“A 2.5-GHz Built-in Jitter Measurement System in a Serial-Link Transceiver,”IEEE Trans. Very Large Scale Integr. Syst.
, vol. 17 , no. 12 , pp. 1698-1708 ,
Dec. 2009
(21) Yu-Lung Lo, Wei-Bin Yang, Ting-Sheng Chao, and Kuo-Hsing Cheng,“High-Speed and Ultra-Low-Voltage Divide-by-4/5 Counter for Frequency Synthesizer,”IEICE Trans. on Electronics
, pp. 0 ,
Jun. 2009 (EI,SCI)
(22) Yu-Lung Lo, Wei-Bin Yang, Ting-Sheng Chao, and Kuo-Hsing Cheng,“Designing an Ultra low-Voltage Phase-Locked Loop Using a Bulk-Driven Technique,”IEEE Trans. Circuits Syst. II, Express Briefs
, vol. 56 , no. 5 , pp. 339-343 ,
May 2009 (EI,SCI)
(23) Shu-Yu Jiang, Chan-Wei Huang, Yu-Lung Lo, and Kuo-Hsing Cheng,“Vernier Caliper and Equivalent-Signal Sampling for Built-in Jitter Measurement System,”IEICE Trans on Fundamentals of Electronics, Communications and Computer Sciences
, pp. 389-400 ,
Jan. 2009 (EI,SCI)
(24) Kuo-Hsing Cheng, Yu-Chang Tsai, Chien-Han Jimmy Liu, Kai-Wei Hong, and Chin-Cheng Kuo,“A low jitter self-calibration PLL for 10-Gbps SoC transmission lines application,”IEICE Trans. Electron
,
Jan. 2009
(25) Kuo-Hsing Cheng, Chia-Wei Su, and Hsin-Hsin Ko,“Highly Accurate and Efficient Current-Mode PWM CMOS DC-DC Buck Converter with On-Chip Current-Sensing,”IEICE Trans. on Electronics
, pp. 1941-1950 ,
Dec. 2008 (EI)
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International Conference Papers 共 107 篇
(51) Kuo-Hsing Cheng, Wei-Bin Yang, and Shu-Chang Kuo, “A Dual-Slope Phase Detector and Charge Pump Architecture to Achieve Fast Locking of Phase-Locked Loops,” in Proc. IEEE International Symposium on Circuits and Systems, Canada,
May. 2004, pp. 777-780 (EI)
(52) Kuo-Hsing Cheng and Yu-Lung Lo, “A FAST-LOCK DLL WITH POWER-ON RESET CIR- CUIT,” in Proc. IEEE International Symposium on Circuits and Systems ,Canada,
May. 2004, pp. 357- 360 (EI)
(53) Kuo-Hsing Cheng, Tsung-Shen Chen, and Ching-Wen Kuo, “High-Accuracy Current Mirror with Low Settling Time,” in Proc. IEEE Midwest Symposium on Circuits and Systems, Egypt,
Dec. 2003, pp. 198-192
(54) Kuo-Hsing Cheng, Chia-Hung Wei, Yu-Wen Chen, “Design of Low-Power Content Addressable Memory Cell,” in Proc. IEEE Midwest Symposium on Circuits and Systems, Egypt,
Dec. 2003, pp. 1447-1450
(55) Kuo-Hsing Cheng, Yu-Lung Lo and Wen-Fang Yu, “A Mixed-Mode Delay-Locked Loop for Wide-Range Operation and Multiphase Clock Generation,” in Proc. IEEE International Workshop on System-on-Chip for Real-Time Applications,
Jun. 2003
(56) Kuo-Hsing Cheng and Yung-Hsiang Lin, “A Dual-Pulse-Clock Double Edge Triggered Flip-Flop for Low Voltage and High Speed Application,” in Proc. Proc. of 2003 IEEE International Symposium on Circuits and Systems, Bangkok, Thailand,
May. 2003
(57) Kuo-Hsing Cheng, Yang-Han Lee and Wei-Chun Chang, “A New Robust Handshake for Asym- metric Asynchronous Micro-Pipelines,” in Proc. Proc. of 2003 IEEE International Symposium on Circuits and Systems,
May. 2003, pp. 25-28
(58) Kuo-Hsing Cheng, Yu-Lung Lo and Wei-Bin Yang, “A Mixed-Mode Delay-Locked Loop for Wide-Range Operation and Multiphase Outputs,” in Proc. Proc. of 2003 IEEE International Symposium on Circuits and Systems, Bangkok, Thailand,
May. 2003, pp. 25-28 (EI)
(59) Kuo-Hsing Cheng, Shu-Yu Jiang and Zong-Shen Chen, “BIST for Clock Jitter Measurement,” in Proc. Proc. of 2003 IEEE International Symposium on Circuits and Systems, Bangkok, Thailand,
May. 2003, pp. 25-28 (EI)
(60) Kuo-Hsing Cheng, Cheng-Yu Chang and Chia-Hung Wei, “A CMOS Charge Pump for Sub-2.0V Operation,” in Proc. IEEE International Symposium on Circuits and Systems, Bangkok, Thailand,
Mar 2003
(61) Kuo-Hsing Cheng, Shu-Chang Kuo, and Chia-Ming Tu, “A Low Noise 2.0GHz CMOS VCO Design,” in Proc. IEEE Midwest Symposium on Circuits and Systems,
2003, pp. 205-208
(62) Kuo-Hsing Cheng and Shun-Wen Cheng, “Influences of Minimum Cut Plane Properties on the Mincut Circuit Partitioning Problems,” in Proc. Proc. of 2002 IEEE International Conference on Elec- tronics, Citcuits and Systems,
Sep. 2002, pp. 375-379
(63) Kuo-Hsing Cheng and Wen-Bin Yang, “A Low Power Wide Operating frequency and High Noise Immunity Half-Digital Phased-locked Loop,” in Proc. Proc. of The Third IEEE Asic Pacific Conference on ASICs, Grand Hotel, Taipei, Taiwan R.O.C,,
Aug. 2002, pp. 40337
(64) Kuo-Hsing Cheng, Wei-Bin Yang and Shyh-Shyuan Sheu, “A CMOS Low Power And High Noise Immunity Voltage Controlled Oscillator,” in Proc. Proc. Of 6th WSEAS International Multiconference on Circuits, Systems, Communications and Computers, Crete Island, Greece,
Jul. 2002, pp. 7001-7003 (EI)
(65) Kuo-Hsing Cheng, Yu-Lung Lo, and Wei-Bin Yang, “A Novel Power-On Reset Circuit Without Capacitor,” in Proc. Proc. Of 6th WSEAS International Multiconference on Circuits, Systems, Communi ca- tions and Computers, Crete Island, Greece,,
Jul. 2002, pp. 7221-7223 (EI)
(66) Kuo-Hsing Cheng, Ta-Wei Liu, Yung-Hsiang Lin, and Jiann-Chyi Rau, “A Low Power All Digital IF-Discriminator Design,” in Proc. Proc. Of 6th WSEAS International Multiconference on Circuits, Systems, Communications and Computers, Crete Island, Greece,
Jul. 2002, pp. 4661-4663 (EI)
(67) Kuo-Hsing Cheng, Chi-Che Chen and Po-Yu Li, “A High Accurate and High Output Impedance Current Mirror,” in Proc. Proc. Of 6th WSEAS International Multiconference on Circuits, Systems, Communications and Computers, Crete Island, Greece,
Jul. 2002, pp. 6981-6983 (EI)
(68) Kuo-Hsing Cheng and Shun-Wen Cheng, “Prioritized Prime Implicant Patterns Puzzle for Novel Logic Synthesis and Optimization,” in Proc. Proc. Joint ASP-DAC and Int’l VLSI Design Banglore India,
Jan. 2002, pp. 159-159
(69) Kuo-Hsing Cheng and Cheng-Yu Chang, “A CMOS Charge Pump For Sub-2.0V Operation,” in Proc. IEEE International ASIC/SOC Conference,
Jan. 2002 (EI)
(70) Kuo-Hsing Cheng and Yu-Jung Chen, “A Novel All Digital Phase Locked Loop (ADPLL) with Ultra Fast Locked Time and High Oscillation Frequency,” in Proc. Proc. of 14th Annul IEEE Inter- national ASIC/SOC Conference 2001, Washingston, D.C.,
Sep. 2001, pp. 139-143
(71) Kuo-Hsing Cheng and Shun-Wen Cheng, “A Study on The Relationship Between Initial Node- Edge Pair Entropy and Mincut Circuit Partitioning,” in Proc. Proc. of 2001 IEEE International Con- ference on Electronics, Citcuits and Systems, Malta,
Sep. 2001, pp. 889-892
(72) Kuo-Hsing Cheng, Tse-Hua Yao, Shu-Yu Jiang and Wei-Bin Yang, “A Difference Detector PFD For Low Jitter PLL,” in Proc. Proc. of 2001 IEEE International Conference on Electronics, Citcuits and Systems, Malta,
Sep. 2001, pp. 43-46
(73) Kuo-Hsing Cheng and Ven-Chieh Hsieh, “A New Logic Synthesis and Optimization Procedure,” in Proc. Proc. of 2001 IEEE International Symposium on Circuits and Systems, Syndey, Australia,
Sep. 2001, pp. 182-185
(74) Kuo-Hsing Cheng, Wen-Shiuan Lee and Yung-Chong Huang, “A 1.2V 500MHz 32-bit Carry- Look-ahead Adder,” in Proc. Proc. of 2001 IEEE International Conference on Electronics Citcuits and Systems, Malta, vol. 2,
Sep. 2001, pp. pp. 765-768
(75) Kuo-Hsing Cheng, Lin-Jiunn Tzou, Wen-Bin Yang and Shyh-Shyuan Sheu, “A CMOS Low Power Voltage Controlled Oscillator with Split-Path Controller,” in Proc. Proc. of 2001 IEEE International Conference on Electronics, Citcuits and Systems, Malta, vol. 1,
Sep. 2001, pp. 421-424
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Patents
(1) 非石英時脈產生器及其運作方法, 台灣, 發明 第I520495號, 劉仁傑 張啟揚 涂祐豪 鄭國興 , 財團法人工業技術研究院 , 2016/02 至 2033/06
(2) Crystal-Less Clock Generator and Operation Method Thereof, 美國, 發明 第9024693號, 劉仁傑 張啟揚 涂祐豪 鄭國興 , 財團法人工業技術研究院, 2014/12 至 2028/12
(3) 電路最小分割和最小任意比例分割的方法, 台灣, 發明 第182649號, 鄭國興 鄭舜文 , 鄭國興 鄭舜文, 2003/07/11 至 2021/3/2
(4) 互補式金氧半電晶體(CMOS)動態邏輯架構, 台灣, 新型 第91732號, 鄭國興 吳重雨 , 行政院 國科會, 1994/07/01 至 2005/2/18
(5) 新型高速四相動態邏輯電路, 日本, 特許 第286678號, 鄭國興 吳重雨 , 行政院 國科會, 1998/12/18 至 2013/7/29
(6) CMOS Dynamic Logic Structure, 美國, 專利號碼：5,378,942, 鄭國興 吳重雨, 行政院 國科會, 1994/1/3 至 2011/1/3