Journal Conference Patents
Journal Papers 共 43 篇
(1) Jen-Chieh Liu, Yo-Hao Tu, Kuo-Hsing Cheng, and Chi-Yang Chang,“Low supply voltage and multiphase all-digital crystal-less clock generator,”IET Circuits, Devices & Syst.
, vol. 12 , no. 6 , pp. 720-725 ,
Aug. 2018 (SCI)
(2) Yo-Hao Tu, Kuo-Hsing Cheng, Man-Ju Lee, and Jen-Chieh Liu,“A power-saving adaptive equalizer with a digital-controlled self-slope detection,”IEEE Trans. Circuits Syst. I, Reg. Papers
, vol. 65 , no. 7 , pp. 2097–2108 ,
Jul. 2018 (EI,SCI)
(3) Yo-Hao Tu, Jen-Chieh Liu, Kuo-Hsing Cheng, and Chih-Hsun Hsu,“A 0.5-V all-digital clock-deskew buffer with I/Q phase outputs,”Analog Integrated Circuits and Signal Processing
, vol. 93 , no. 1 , pp. 157–167 ,
Oct. 2017 (SCI)
(4) Chih-Wei Tsai, Yu-Lung Lo, Chia-Chen Chang, Han-Ying Liu, Wei-Bin Yang, and Kuo-Hsing Cheng,“All-digital duty-cycle corrector with synchronous and high accuracy output for double date rate synchronous dynamic random-access memory application,”Japanese J. of Appl. Physics
, vol. 56 , no. 4S , pp. 04CF02-1 - 04CF02-6 ,
Jan. 2017
(5) Yo-Hao Tu, Jen-Chieh Liu, and Kuo-Hsing Cheng,“Proportional static-phase-error reduction for frequency-multiplier-based delay-locked-loop architecture,”IEICE Trans. on Electronics
, vol. E99-C , no. 6 , pp. 655-658 ,
Jan. 2016 (SCI)
(6) Yo-Hao Tu, Jen-Chieh Liu, Kuo-Hsing Cheng, Hong-Yi Huang, and Chang-Chien Hu,“A 0.6-V 1.6-GHz 8-phase all digital PLL using multi-phase based TDC,”IEICE Electronic Express
, vol. 13 , no. 2 , pp. 1-12 ,
Jan. 2016 (SCI)
(7) Kuo-Hsing Cheng, Cheng-Liang Hung, Alex Gong C.-S., Jen-Chieh Liu, Bo-Qian Jiang and Shi-Yang Sun,“A 0.9- to 8-GHz VCO with a differential active inductor for multistandard wireline SerDes,”IEEE Trans. Circuits Syst. II, Express Briefs
, vol. 61 , no. 8 , pp. 559-563 ,
Aug. 2014 (EI,SCI)
(8) Kuo-Hsing Cheng, Jen-Chieh Liu, and Hong-Yi Huang,“A 0.6-V 800-MHz All-Digital Phase-Locked Loop with a Digital Supply Regulator,”IEEE Trans. Circuits Syst. II, Express Briefs
, vol. 59 , no. 12 , pp. 888 - 892 ,
Dec. 2012 (EI,SCI)
(9) Kuo-Hsing Cheng, Kai-Wei Hong, Chi-Fa Hsu, and Bo-Qian Jiang ,“An All-Digital Clock Synchronization Buffer With One Cycle Dynamic Synchronizing,”IEEE Trans. Very Large Scale Integr. Syst.
, vol. 20 , no. 10 , pp. 1818-1827 ,
Oct. 2012 (EI,SCI)
(10) Shyh-Shyuan Sheu, Kuo-Hsing Cheng, Yu-Sheng Chen, Pang-Shiu Chen, Ming-Jinn Tsai, and Yu-Lung Lo,“A 50ns Verify Speed in Resistive random access memory by using a Write Resistance Tracking Circuit,”IEICE TRANSACTIONS ON ELECTRONICS
, vol. E95-C , no. 6 , pp. 1128-1131 ,
Jun. 2012 (SCI)
(11) Jen-Chieh Liu, Hong-Yi Huang, and Kuo-Hsing Cheng,“A 0.3 Volt All Digital Crystal-less Clock Generator,”ICL Technical Journal
, vol. 143 , no. 2 , pp. 126-133 ,
Feb. 2012
(12) Kuo-Hsing Cheng, Jen-Chieh Liu, and Hong-Yi Huang,“A 6-GHz Built-in Jitter Measurement Circuit Using Multiphase Sampler,”IEEE Trans. Circuits Syst. II, Express Briefs
, vol. 58 , no. 8 , pp. 492 ,
Aug. 2011 (EI,SCI)
(13) Kuo-Hsing Cheng, Kai-Wei Hong, Chi-Hsiang Chen, and Jen-Chieh Liu,“A High Precision Fast Locking Arbitrary Duty Cycle Clock Synchronization Circuit,”IEEE Trans. Very Large Scale Integr. Syst.
, vol. 19 , no. 7 , pp. 1218-1228 ,
Jul. 2011 (EI,SCI)
(14) Kuo-Hsing Cheng, Cheng-Liang Hung, and Chih-Hsien Chang,“A 0.77 ps RMS Jitter 6-GHz Spread-Spectrum Clock Generator Using a Compensated Phase-Rotating Technique,”IEEE J. Solid-State Circuits
, vol. 46 , no. 5 , pp. 1198-1213 ,
May 2011 (EI,SCI)
(15) Kuo-Hsing Cheng, Yu-Chang Tsai, Yu-Lung Lo, and Jing-Shiuan Huang,“A 0.5-V 0.4–2.24-GHz Inductorless Phase-Locked Loop in a System-on-Chip ,”IEEE Trans. Circuits Syst. I, Reg. Papers
, vol. 58 , no. 5 , pp. 849 ,
May 2011 (EI,SCI)
(16) Shyh-Shyuan Sheu and Kuo-Hsing Cheng,“Fast-Write Resistive RAM (RRAM) for Embedded Applications,”IEEE Design & Test of Computers
, vol. 28 , pp. 64-71 ,
Feb. 2011
(17) Kuo-Hsing Cheng, Kai-Wei Hong, Yu-Lung Lo, Chen-Lung Wu and Chien-Hsien Lee,“Dynamic frequency tracking and phase error compensation clock de-skew buffer,”IEE Electronics Letters
, vol. 46 , no. 25 , pp. 1653-1655 ,
Dec. 2010 (EI,SCI)
(18) Kuo-Hsing Cheng, Jen-Chieh Liu, Chih-Yu Chang, Shu-Yu Jiang, and Kai-Wei Hong,“Built-in Jitter Measurement Circuit with Calibration Techniques for a 3 GHz Clock Generator,”IEEE Trans. Very Large Scale Integr. Syst.
, pp. 1325-1335 ,
Jun. 2010 (EI,SCI)
(19) Kuo-Hsing Cheng, Yu-Chang Tsai, Yen-Hsueh Wu, and Ying-Fu Lin,“A 5Gb/s Inductorless CMOS Adaptive Equalizer for PCI Express Generation II Applications,”IEEE Trans. Circuits Syst. II, Express Briefs
, pp. 324-328 ,
May 2010 (EI,SCI)
(20) Kuo-Hsing Cheng, Shu-Yu Jiang, and Pei-Yi Jian,“A 2.5-GHz Built-in Jitter Measurement System in a Serial-Link Transceiver,”IEEE Trans. Very Large Scale Integr. Syst.
, vol. 17 , no. 12 , pp. 1698-1708 ,
Dec. 2009
(21) Yu-Lung Lo, Wei-Bin Yang, Ting-Sheng Chao, and Kuo-Hsing Cheng,“High-Speed and Ultra-Low-Voltage Divide-by-4/5 Counter for Frequency Synthesizer,”IEICE Trans. on Electronics
, pp. 0 ,
Jun. 2009 (EI,SCI)
(22) Yu-Lung Lo, Wei-Bin Yang, Ting-Sheng Chao, and Kuo-Hsing Cheng,“Designing an Ultra low-Voltage Phase-Locked Loop Using a Bulk-Driven Technique,”IEEE Trans. Circuits Syst. II, Express Briefs
, vol. 56 , no. 5 , pp. 339-343 ,
May 2009 (EI,SCI)
(23) Shu-Yu Jiang, Chan-Wei Huang, Yu-Lung Lo, and Kuo-Hsing Cheng,“Vernier Caliper and Equivalent-Signal Sampling for Built-in Jitter Measurement System,”IEICE Trans on Fundamentals of Electronics, Communications and Computer Sciences
, pp. 389-400 ,
Jan. 2009 (EI,SCI)
(24) Kuo-Hsing Cheng, Yu-Chang Tsai, Chien-Han Jimmy Liu, Kai-Wei Hong, and Chin-Cheng Kuo,“A low jitter self-calibration PLL for 10-Gbps SoC transmission lines application,”IEICE Trans. Electron
,
Jan. 2009
(25) Kuo-Hsing Cheng, Chia-Wei Su, and Hsin-Hsin Ko,“Highly Accurate and Efficient Current-Mode PWM CMOS DC-DC Buck Converter with On-Chip Current-Sensing,”IEICE Trans. on Electronics
, pp. 1941-1950 ,
Dec. 2008 (EI)
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International Conference Papers 共 107 篇
(26) Kuo-Hsing Cheng, Chia-Wei Su, Meng-Jhe Wu, and Yu-Ling Chang,, “A wide-range DLL-based clock generator with phase error calibration,” in Proc. IEEE International Conference on Electronics, Circuits and Systems, ICECS,
Aug. 2008, pp. 798 - 801 (EI)
(27) Kuo-Hsing Cheng, Yu-Chang Tsai, Kai-Wei Hong, and Yen-Hsueh Wu,, “A Low Jitter Self-Calibration PLL for 10Gbps SoC Transmission Links Application,” in Proc. IEEE International Conference on Electronics, Circuits and Systems, ICECS,
Aug. 2008, pp. 786 - 789 (EI)
(28) Ci-Tong Hong,Kai-Wen Yao, Muh-Tian Shiue, and Kuo-Hsing Cheng, “A Compact and Low-Power SRAM with Improved Read Static Noise Margin,” in Proc. IEEE International Conference on Electronics, Circuits and Systems, ICECS,
Aug. 2008, pp. 546 - 549 (EI)
(29) Kuo-Hsing Cheng, Hsin-Hao Wang, Ding-Jyun Huang, “A 1-V 10-bit 2GSample/s D/A converter based on precision current reference in 90-nm CMOS,” in Proc. IEEE Trans. Circuits Syst. I, Reg. Papers,
Aug. 2008, pp. 340-343
(30) Kuo-Hsing Cheng, Cheng-Liang Hung, Chih-Hsien Chang, Yu-Lung Lo, Wei-Bin Yang, and Jiunn-Way Miaw, “A Spread-Spectrum Clock Generator Using Fractional-N PLL Controlled Delta-Sigma Modulator for Serial-ATA III,” in Proc. IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems,
Apr. 2008, pp. 1-4
(31) Hong-Yi Huang, Jen-Chieh Liu and Kuo-Hsing Cheng, “All-Digital PLL Using Pulse-Based DCO,” in Proc. IEEE International Conference on Electronics, Circuits and Systems,
Dec. 2007, pp. 1268-1271
(32) Kuo-Hsing Cheng, Pei-Kai Tseng, and Yu-Lung Lo, “A Phase Interpolator For Sub-1V And High Frequecy For Clock And Data Recovery,” in Proc. IEEE International Conference on Electronics, Circuits and Systems,
Dec. 2007, pp. 363-366
(33) Kuo-Hsing Cheng, Yu-Lung Lo, Ching-Wen Lai, and Wei-Bin Yang, “A 100MHz-1GHz Adaptive Bandwith PLL Using TDC Technique,” in Proc. IEEE International Conference on Electronics, Circuits and Systems,
Dec. 2007, pp. 1163-1166
(34) Kuo-Hsing Cheng, Cheng-Liang Hung, and Chia-Wei Su, “A Sub-1V Low-Power High-Speed Static Frequency Divider,” in Proc. IEEE International Symposium on Circuits and Systems,
May. 2007, pp. 3848-3851 (EI)
(35) Kuo-Hsing Cheng, Chao-An Chen, Wei-Bin Yang, and Feng-Hsin Cho, “A 30Phase 500MHZ PLL For 3X Over-Sampling Clock Data Recovery,” in Proc. IEEE International Symposium on VLSI Design, Automation and Test,
Apr. 2007, pp. 1月4日 (EI)
(36) Kuo-Hsing Cheng, Kai-Wei Hung, Chien-Hsien Lee and Chen-Lung Wu, “A Variable Duty Cycle with High-Resolution Synchronous Mirror Delay,” in Proc. IEEE International Conference on Electronics, Circuits and Systems,
Dec. 2006, pp. 569-572
(37) Kuo-Hsing Cheng, Cheng-Liang Hung and Chen-Lung Wu, “Arbitrary Duty Cycle Synchronous Mirror Delay Circuits Design,” in Proc. IEEE Asian Solid-State Circuits Conference,
Nov. 2006, pp. 283-286 (EI)
(38) Kuo-Hsing Cheng, Chia-Wei Su , Kai-Fei Chang, Cheng-Liang Hung and Wei-Bin Yang, “A High Linearity and Fast-Locked PulseWidth Control Loop with Digitally Programmable Output Duty Cycle for Wide Range Operation,” in Proc. IEEE European Solid-State Circuits Conference,
Sep. 2006, pp. 178-181
(39) Kuo-Hsing Cheng, Chan-Wei Huang and Shu-Yu Jiang, “Self-sampled vernier delay line for built-in clock jitter measurement,” in Proc. IEEE International Symposium on Circuits and Systems,
May. 2006, pp. 1591-1594 (EI)
(40) Kuo-Hsing Cheng, Kai-Fei Chang, Yu-Lung Lo, Ching-Wen Lai and Yuh-Kuang Tseng, “A 100- MHz-1GHz adaptive bandwidth phase-locked loop in 90nm process,” in Proc. IEEE International Symposium on Circuits and Systems,
May. 2006, pp. 3205-3208 (EI)
(41) Kuo-Hsing Cheng and Yu-Lung Lo, “A fast-lock mixed-mode DLL with wide-range operation and multiphase outputs,” in Proc. IEEE Design, Automation and Test in Europe,
Mar 2006, pp. 6-10 (EI)
(42) Kuo-Hsing Cheng and Yu-Lung Lo, “A fast-lock mixed-mode DLL with wide-range operation and multiphase outputs,” in Proc. IEEE European Solid-State Circuits Conference,
Sep. 2005, pp. 189-192
(43) Kuo-Hsing Cheng, Shu-Ming Chang, Shu-Yu Jiang and Wei-Bin Yang, “A 2GHZ Fully Differential DLL-based Frequency Multiplier for High Speed Serial Link Circuit,” in Proc. IEEE International Symposium on Circuits and Systems, Japan,
May. 2005, pp. 1174-1177 (EI)
(44) Kuo-Hsing Cheng, Chen-Lung Wu, Yu-Lung Lo and Chia-Wei Su, “A Phase-detect Synchronous Mirror Delay for Fast Clock Skew-compensation Circuits,” in Proc. IEEE International Symposium on Circuits and Systems, Japan,
May. 2005, pp. 1070-1073
(45) Kuo-Hsing Cheng and Shu-Yu Jiang, “High Accuracy jitter measurement using cyclic pulse width modulation structure,” in Proc. IEEE International Symposium on VLSI Design, Automation and Test,
Apr. 2005, pp. 24-27 (EI)
(46) Kuo-Hsing Cheng, Chia-Wei Su, Chen-Lung Wu and Yu-Lung Lo, “A Phase-Locked Pulse Width Control Loop with Programmable Duty Cycle,” in Proc. IEEE Asia-Pacific Conference on Advanced System Integrated Circuits,
Aug. 2004, pp. 84-87 (EI)
(47) Kuo-Hsing Cheng, Shu-Ming Chang, Yu-Lung Lo and Shu-Yu Jiang, “A 2.2GHz Programmable DLL-Based Frequency Multiplier for SOC Application,” in Proc. IEEE Asia-Pacific Conference on Ad- vanced System Integrated Circuits, Japan,
Aug. 2004, pp. 72-75 (EI)
(48) Kuo-Hsing Cheng, Ching-Wen Lai and Yu-Lung Lo, “A CMOS VCO for 1V, 1GHz PLL Applica- tions,” in Proc. IEEE Asia-Pacific Conference on Advanced System Integrated Circuits, Japan,
Aug. 2004, pp. 150- 153 (EI)
(49) Kuo-Hsing Cheng, Tsung-Shen Chen, and Chia Ming Tu, “A 14-Bit, 200MS/S Digital-to-Analog Converter without Trimming,” in Proc. IEEE International Symposium on Circuits and Systems, Canada,
May. 2004, pp. 353-358 (EI)
(50) Kuo-Hsing Cheng, Chia-Hung Wei, Shu-Yu Jiang, “Static divided word matching line for low power content addressable memory design,” in Proc. IEEE International Symposium on Circuits and Systems, Canada,
May. 2004, pp. 629-632 (EI)
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Patents
(1) 非石英時脈產生器及其運作方法, 台灣, 發明 第I520495號, 劉仁傑 張啟揚 涂祐豪 鄭國興 , 財團法人工業技術研究院 , 2016/02 至 2033/06
(2) Crystal-Less Clock Generator and Operation Method Thereof, 美國, 發明 第9024693號, 劉仁傑 張啟揚 涂祐豪 鄭國興 , 財團法人工業技術研究院, 2014/12 至 2028/12
(3) 電路最小分割和最小任意比例分割的方法, 台灣, 發明 第182649號, 鄭國興 鄭舜文 , 鄭國興 鄭舜文, 2003/07/11 至 2021/3/2
(4) 互補式金氧半電晶體(CMOS)動態邏輯架構, 台灣, 新型 第91732號, 鄭國興 吳重雨 , 行政院 國科會, 1994/07/01 至 2005/2/18
(5) 新型高速四相動態邏輯電路, 日本, 特許 第286678號, 鄭國興 吳重雨 , 行政院 國科會, 1998/12/18 至 2013/7/29
(6) CMOS Dynamic Logic Structure, 美國, 專利號碼：5,378,942, 鄭國興 吳重雨, 行政院 國科會, 1994/1/3 至 2011/1/3