Journal Conference Patents
Journal Papers 共 43 篇
(1) Jen-Chieh Liu, Yo-Hao Tu, Kuo-Hsing Cheng, and Chi-Yang Chang,“Low supply voltage and multiphase all-digital crystal-less clock generator,”IET Circuits, Devices & Syst.
, vol. 12 , no. 6 , pp. 720-725 ,
Aug. 2018 (SCI)
(2) Yo-Hao Tu, Kuo-Hsing Cheng, Man-Ju Lee, and Jen-Chieh Liu,“A power-saving adaptive equalizer with a digital-controlled self-slope detection,”IEEE Trans. Circuits Syst. I, Reg. Papers
, vol. 65 , no. 7 , pp. 2097–2108 ,
Jul. 2018 (EI,SCI)
(3) Yo-Hao Tu, Jen-Chieh Liu, Kuo-Hsing Cheng, and Chih-Hsun Hsu,“A 0.5-V all-digital clock-deskew buffer with I/Q phase outputs,”Analog Integrated Circuits and Signal Processing
, vol. 93 , no. 1 , pp. 157–167 ,
Oct. 2017 (SCI)
(4) Chih-Wei Tsai, Yu-Lung Lo, Chia-Chen Chang, Han-Ying Liu, Wei-Bin Yang, and Kuo-Hsing Cheng,“All-digital duty-cycle corrector with synchronous and high accuracy output for double date rate synchronous dynamic random-access memory application,”Japanese J. of Appl. Physics
, vol. 56 , no. 4S , pp. 04CF02-1 - 04CF02-6 ,
Jan. 2017
(5) Yo-Hao Tu, Jen-Chieh Liu, and Kuo-Hsing Cheng,“Proportional static-phase-error reduction for frequency-multiplier-based delay-locked-loop architecture,”IEICE Trans. on Electronics
, vol. E99-C , no. 6 , pp. 655-658 ,
Jan. 2016 (SCI)
(6) Yo-Hao Tu, Jen-Chieh Liu, Kuo-Hsing Cheng, Hong-Yi Huang, and Chang-Chien Hu,“A 0.6-V 1.6-GHz 8-phase all digital PLL using multi-phase based TDC,”IEICE Electronic Express
, vol. 13 , no. 2 , pp. 1-12 ,
Jan. 2016 (SCI)
(7) Kuo-Hsing Cheng, Cheng-Liang Hung, Alex Gong C.-S., Jen-Chieh Liu, Bo-Qian Jiang and Shi-Yang Sun,“A 0.9- to 8-GHz VCO with a differential active inductor for multistandard wireline SerDes,”IEEE Trans. Circuits Syst. II, Express Briefs
, vol. 61 , no. 8 , pp. 559-563 ,
Aug. 2014 (EI,SCI)
(8) Kuo-Hsing Cheng, Jen-Chieh Liu, and Hong-Yi Huang,“A 0.6-V 800-MHz All-Digital Phase-Locked Loop with a Digital Supply Regulator,”IEEE Trans. Circuits Syst. II, Express Briefs
, vol. 59 , no. 12 , pp. 888 - 892 ,
Dec. 2012 (EI,SCI)
(9) Kuo-Hsing Cheng, Kai-Wei Hong, Chi-Fa Hsu, and Bo-Qian Jiang ,“An All-Digital Clock Synchronization Buffer With One Cycle Dynamic Synchronizing,”IEEE Trans. Very Large Scale Integr. Syst.
, vol. 20 , no. 10 , pp. 1818-1827 ,
Oct. 2012 (EI,SCI)
(10) Shyh-Shyuan Sheu, Kuo-Hsing Cheng, Yu-Sheng Chen, Pang-Shiu Chen, Ming-Jinn Tsai, and Yu-Lung Lo,“A 50ns Verify Speed in Resistive random access memory by using a Write Resistance Tracking Circuit,”IEICE TRANSACTIONS ON ELECTRONICS
, vol. E95-C , no. 6 , pp. 1128-1131 ,
Jun. 2012 (SCI)
(11) Jen-Chieh Liu, Hong-Yi Huang, and Kuo-Hsing Cheng,“A 0.3 Volt All Digital Crystal-less Clock Generator,”ICL Technical Journal
, vol. 143 , no. 2 , pp. 126-133 ,
Feb. 2012
(12) Kuo-Hsing Cheng, Jen-Chieh Liu, and Hong-Yi Huang,“A 6-GHz Built-in Jitter Measurement Circuit Using Multiphase Sampler,”IEEE Trans. Circuits Syst. II, Express Briefs
, vol. 58 , no. 8 , pp. 492 ,
Aug. 2011 (EI,SCI)
(13) Kuo-Hsing Cheng, Kai-Wei Hong, Chi-Hsiang Chen, and Jen-Chieh Liu,“A High Precision Fast Locking Arbitrary Duty Cycle Clock Synchronization Circuit,”IEEE Trans. Very Large Scale Integr. Syst.
, vol. 19 , no. 7 , pp. 1218-1228 ,
Jul. 2011 (EI,SCI)
(14) Kuo-Hsing Cheng, Cheng-Liang Hung, and Chih-Hsien Chang,“A 0.77 ps RMS Jitter 6-GHz Spread-Spectrum Clock Generator Using a Compensated Phase-Rotating Technique,”IEEE J. Solid-State Circuits
, vol. 46 , no. 5 , pp. 1198-1213 ,
May 2011 (EI,SCI)
(15) Kuo-Hsing Cheng, Yu-Chang Tsai, Yu-Lung Lo, and Jing-Shiuan Huang,“A 0.5-V 0.4–2.24-GHz Inductorless Phase-Locked Loop in a System-on-Chip ,”IEEE Trans. Circuits Syst. I, Reg. Papers
, vol. 58 , no. 5 , pp. 849 ,
May 2011 (EI,SCI)
(16) Shyh-Shyuan Sheu and Kuo-Hsing Cheng,“Fast-Write Resistive RAM (RRAM) for Embedded Applications,”IEEE Design & Test of Computers
, vol. 28 , pp. 64-71 ,
Feb. 2011
(17) Kuo-Hsing Cheng, Kai-Wei Hong, Yu-Lung Lo, Chen-Lung Wu and Chien-Hsien Lee,“Dynamic frequency tracking and phase error compensation clock de-skew buffer,”IEE Electronics Letters
, vol. 46 , no. 25 , pp. 1653-1655 ,
Dec. 2010 (EI,SCI)
(18) Kuo-Hsing Cheng, Jen-Chieh Liu, Chih-Yu Chang, Shu-Yu Jiang, and Kai-Wei Hong,“Built-in Jitter Measurement Circuit with Calibration Techniques for a 3 GHz Clock Generator,”IEEE Trans. Very Large Scale Integr. Syst.
, pp. 1325-1335 ,
Jun. 2010 (EI,SCI)
(19) Kuo-Hsing Cheng, Yu-Chang Tsai, Yen-Hsueh Wu, and Ying-Fu Lin,“A 5Gb/s Inductorless CMOS Adaptive Equalizer for PCI Express Generation II Applications,”IEEE Trans. Circuits Syst. II, Express Briefs
, pp. 324-328 ,
May 2010 (EI,SCI)
(20) Kuo-Hsing Cheng, Shu-Yu Jiang, and Pei-Yi Jian,“A 2.5-GHz Built-in Jitter Measurement System in a Serial-Link Transceiver,”IEEE Trans. Very Large Scale Integr. Syst.
, vol. 17 , no. 12 , pp. 1698-1708 ,
Dec. 2009
(21) Yu-Lung Lo, Wei-Bin Yang, Ting-Sheng Chao, and Kuo-Hsing Cheng,“High-Speed and Ultra-Low-Voltage Divide-by-4/5 Counter for Frequency Synthesizer,”IEICE Trans. on Electronics
, pp. 0 ,
Jun. 2009 (EI,SCI)
(22) Yu-Lung Lo, Wei-Bin Yang, Ting-Sheng Chao, and Kuo-Hsing Cheng,“Designing an Ultra low-Voltage Phase-Locked Loop Using a Bulk-Driven Technique,”IEEE Trans. Circuits Syst. II, Express Briefs
, vol. 56 , no. 5 , pp. 339-343 ,
May 2009 (EI,SCI)
(23) Shu-Yu Jiang, Chan-Wei Huang, Yu-Lung Lo, and Kuo-Hsing Cheng,“Vernier Caliper and Equivalent-Signal Sampling for Built-in Jitter Measurement System,”IEICE Trans on Fundamentals of Electronics, Communications and Computer Sciences
, pp. 389-400 ,
Jan. 2009 (EI,SCI)
(24) Kuo-Hsing Cheng, Yu-Chang Tsai, Chien-Han Jimmy Liu, Kai-Wei Hong, and Chin-Cheng Kuo,“A low jitter self-calibration PLL for 10-Gbps SoC transmission lines application,”IEICE Trans. Electron
,
Jan. 2009
(25) Kuo-Hsing Cheng, Chia-Wei Su, and Hsin-Hsin Ko,“Highly Accurate and Efficient Current-Mode PWM CMOS DC-DC Buck Converter with On-Chip Current-Sensing,”IEICE Trans. on Electronics
, pp. 1941-1950 ,
Dec. 2008 (EI)
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International Conference Papers 共 107 篇
(76) Kuo-Hsing Cheng, Chi-Che Chen and Po-Yu Li, “Accurate Current Mirror with High Output Impedance,” in Proc. Proc. Of 6th WSEAS International Multiconference on Circuits, Systems, Communications and Computers, Crete Island, Greece,
Jul. 2001, pp. 565-568 (EI)
(77) Kuo-Hsing Cheng, Wei-Bin Yang, and Chun-Fu Chung, “A Low-Power High Driving Ability Voltage Control Oscillator Used in PLL,” in Proc. Proc. of 2001 IEEE International Symposium on Circuits and Systems, Syndey, Australia,
May. 2001, pp. 614-617
(78) Kuo-Hsing Cheng and Shun-Wen Cheng, “Enisle: An Optimal and Intuitive Heuristic Nearly Optimal Solution for Mincut and Ratio Mincut Partitioning,” in Proc. Proc. of 2001 IEEE International Symposium on Circuits and Systems, Syndey, Australia,
Mar 2001, pp. 167-170 (ISCAS)
(79) Kuo-Hsing Cheng and Yung-Chong Huang, “The Non-full Voltage Swing TSPC (NSTSPC) Logic Design,” in Proc. Proc. of IEEE ASIA-PACIFIC Conference on ASIC, Cheju, Korea,
Aug. 2000
(80) Kuo-Hsing Cheng and Chun-Pin Lin, “The Design and Implementation of DCT/IDCT Chip With Novel Architecture,” in Proc. Proc. of 2000 IEEE International Symposium on Circuits and Systems, Geneva, Switzerland,
May. 2000, pp. 741-744
(81) Kuo-Hsing Cheng and Lin-Jiun Tzou, “A Low-Jitter and Low-Power Phase-Locked Loop De-sign,” in Proc. Proc. of 2000 IEEE International Symposium on Circuits and Systems, Geneva,Switzerland,,
May. 2000, pp. 257-260
(82) Kuo-Hsing Cheng and Chih-Sheng Huang, “The Novel Efficient Design of XOR/XNOR Function for Adder Applications,” in Proc. Proc. of The 6th IEEE International Conference on Electronics, Circuits, and Systems, Pafos, Cyprus,
Sep. 1999, pp. 29-32
(83) Kuo-Hsing Cheng and Wei-Bin Yang, “The Suggestion for CFS CMOS Buffer,” in Proc. Proc. of The 6th IEEE International Conference on Electronics Circuits and Systems, Pafos, Cyprus,
Sep. 1999, pp. 779-802
(84) Kuo-Hsing Cheng and Ven-Chieh Hsieh, “High Efficient 3-input XOR for Low-Voltage Low- Power High Speed Applications,” in Proc. Proc. of The First IEEE Asic Pacific Conference on ASICs, Seoul, Koreal,
Aug. 1999, pp. 166-169
(85) Kuo-Hsing Cheng and Huan-Sen Liao, “A Programmable Delay Element for Low Power PLL Applications,” in Proc. Proc. of 1999 International Analog VLSI Workshop,
May. 1999, pp. 67-71
(86) Kuo-Hsing Cheng, Tsong-Liang Huang, and Chih-Sheng Huang, “The Design and Analysis of Pass-Transistor Logic for Low Power Applications,” in Proc. Proc. of 1998 International Conference On ASIC, Beijinng,
Oct. 1998, pp. 253-256
(87) Kuo-Hsing Cheng, Shu-Min Chiang, and Shun-Wen Cheng, “The Improvement of Conditional Sum Adder for Low Power Applications,” in Proc. Proc. of 1998 IEEE International ASIC Conference, New York,
Sep. 1998, pp. 131-134
(88) Kuo-Hsing Cheng, Yu-Kwang Yeha, and Farn-Son Lian, “Low Voltage Low Power High-Speed BiCMOS Multiplier,” in Proc. Proc. of 1998 IEEE International Conference on Electronics, Circuits, and Systems, Lisbon, Portugal,
Sep. 1998, pp. 49-50
(89) Kuo-Hsing Cheng, and Yu-Hsiang Chen, “Low-Power All Digital Down Connverter for IS-95 Forward Link Demodulation,” in Proc. Proc. of 1998 International Symposium on Nonlinear Theory and its Applications, Crans-Montana, Switzerlannd,
Sep. 1998, pp. 425-428
(90) Kuo-Hsing Cheng, and Cheng-Chung Sun, “An Efficient FIR Filter Design for VLSI Implemen- tation,” in Proc. Proc. of 1998 International Symposium on Nonlinear Theory and its Applications, Crans-Montana, Switzerlannd,
Sep. 1998, pp. 815-818
(91) Kuo-Hsing Cheng, and Huan-Sen Liao, “A Linear Current Controlled Delay Element for Low Power Applications,” in Proc. Proc. of 1998 International Symposium on Nonlinear Theory and its Appli- cations, Crans-Montana, Switzerlannd,
Jan. 1998, pp. 421-424
(92) Kuo-Hsing Cheng and Wei-Bin Yang, “The Charge Transfer Feedback-Controlled Split Path CMOS Buffer,” in Proc. Proc. of IEEE International Conference on Electronics, Circuits, and Systems, Cairo, Egypt,
Dec. 1997, pp. 828-285
(93) Kuo-Hsing Cheng and Jian-Hung Chen, “1.2V Low-Power TSPC Complementary Pass-Tran- sistor Logic,” in Proc. Proc. of IEEE International Conference on Electronics, Circuits, and Systems, Cairo, Egypt,
Dec. 1997, pp. 1445-1448
(94) Kuo-Hsing Cheng and Wei-Bin Yang, “Low-Voltage-Swing Low-Power CMOS Buffer,” in Proc. Proc. of 1997 International Symposium on Nonlinear Theory and its Applications, Hilton Hawaiian Village, Hawaii,
Nov. 1997, pp. 821-824
(95) Kuo-Hsing Cheng, Jian-Hung Chen, “1.2V Low-Power Dynamic omplementary-Pass- Transistor Logic,” in Proc. Proc. of 1997 International Symposium on Nonlinear Theory and its Appli- cations, Hilton Hawaiian Village, Hawaii,
Nov. 1997, pp. 817-820
(96) Kuo-Hsing Cheng,Huei-Chi Wang, “Design of Current Mode Operational Amplifier with Differential-Input and Differential-Output,” in Proc. Proc. of 1997 IEEE International Symposium on Circuits and Systems, Hong Kong,
Jun. 1997, pp. 153-156
(97) Kuo-Hsing Cheng, (Yii-Yih Liaw) Liow Yu Yee,Jian-Hung Chen, “A Suggestion for Low- Power Current-Sensing Complementary Pass-Transistor Logic Interconnection,” in Proc. Proc. of 1997 IEEE International Symposium on Circuits and Systems, Hong Kong,
Jun. 1997, pp. 1948-1951 (EI)
(98) Kuo-Hsing Cheng,Liow Yu Yee, “A 1.2 CMOS Multiplier Using Low Power Current-Sensing Complementary Pass-Transistor Logic,” in Proc. Proc. of Third IEEE International Conference on Electronics Circuits and Systems, Rodos, Greece,
Oct. 1996, pp. 1037-1040 (EI)
(99) Kuo-Hsing Cheng and Yii-Yih Liaw, “A Low Power Current-Sensing Complementary Pass- Transistor Logic (LCSCPTL) for Low-Voltage High-Speed Applications,” in Proc. Proc. of 1996 Symposium on VLSI Circuits,
Jun. 1996, pp. 16-17
(100) Hong-Yi Huang, Kuo-Hsing Cheng, Yuan-Hua Chu, and Chung-Yu Wu, “True-Single-Phase All-N-Logic Differential Logic (TADL) for Very High-Speed Complex VLSI,” in Proc. Proc. of 1996 IEEE International Symposium on Circuits and Systems, Atlanta , U.S.A,
May. 1996, pp. 1037-1040
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Patents
(1) 非石英時脈產生器及其運作方法, 台灣, 發明 第I520495號, 劉仁傑 張啟揚 涂祐豪 鄭國興 , 財團法人工業技術研究院 , 2016/02 至 2033/06
(2) Crystal-Less Clock Generator and Operation Method Thereof, 美國, 發明 第9024693號, 劉仁傑 張啟揚 涂祐豪 鄭國興 , 財團法人工業技術研究院, 2014/12 至 2028/12
(3) 電路最小分割和最小任意比例分割的方法, 台灣, 發明 第182649號, 鄭國興 鄭舜文 , 鄭國興 鄭舜文, 2003/07/11 至 2021/3/2
(4) 互補式金氧半電晶體(CMOS)動態邏輯架構, 台灣, 新型 第91732號, 鄭國興 吳重雨 , 行政院 國科會, 1994/07/01 至 2005/2/18
(5) 新型高速四相動態邏輯電路, 日本, 特許 第286678號, 鄭國興 吳重雨 , 行政院 國科會, 1998/12/18 至 2013/7/29
(6) CMOS Dynamic Logic Structure, 美國, 專利號碼：5,378,942, 鄭國興 吳重雨, 行政院 國科會, 1994/1/3 至 2011/1/3