Journal Conference Patents
Journal Papers 共 43 篇
(26) Kuo-Hsing Cheng, Chia-Wei Su, and Siao-Wun Lu,“Wide-range synchronous mirror delay with arbitrary input duty cycle,”IEE ELECTRONICS LETTERS
, vol. 44 , no. 11 , pp. 655-667 ,
May 2008 (EI,SCI)
(27) Kuo-Hsing Cheng, Chia-Wei Su, and Kai-Fei Chang,“A High Linearity, Fast-Locking PulseWidth Control Loop with Digitally Programmable Duty Cycle Correction for Wide Range Operation,”IEEE J. Solid State Circuits
, vol. 43 , pp. 399-413 ,
Feb. 2008 (EI,SCI)
(28) Kuo-Hsing Cheng, and Yu-Lung Lo,“A Fast-Lock Wide-Range Delay-Locked Loop Using Frequency-Range Selector for Multiphase Clock Generator,”IEEE Trans. On Circuits and Systems II
, vol. 54 , pp. 561-565 ,
Jul. 2007 (EI,SCI)
(29) Tseng-Hsin Chiu, Tung-Wuu Huang, Chung-Hsi Liang, Dow-Chieh Niu, Yuen-Wuu Suen, and Kuo-Hsing Cheng,“Attenuation of Electromagnetic Pulse Using High Temperature Superconductor,”IEEE Transactions on applied superconductivity
, vol. 17 , pp. 1831-1834 ,
Jun. 2007 (EI,SCI)
(30) Kuo-Hsing Cheng, Shun-Wen Cheng, and Wen-Shiuan Lee,“64-bit Pipeline Carry Lookahead Adder using ALL-N-Transistor TSPC Logics,”Journal of Circuits Systems and Computers
, vol. 15 , no. 1 , pp. 13-27 ,
Jan. 2006 (EI,SCI)
(31) Kuo-Hsing Cheng, and Shun -Wen Cheng,“Improved 32-bit Conditional Sum Adder for Low-Power High-Speed Applications,”Journal of Information Science and Engineering
, vol. 22 , pp. 975-990 ,
Jul. 2005 (SCI,EI)
(32) Kuo-Hsing Cheng, and Shun-Wen Cheng,“A Clustering Algorithm for Nearly Maximal and Minimal Connection on Hypergraph,”Tamkang Journal of Science and Engineering
, vol. 8 , no. 2 , pp. 155–164 ,
Jun. 2005 (EI)
(33) Kuo-Hsing Cheng, and Shun-Wen Cheng,“64-bit High-Performance Power-Aware Conditional Carry Adder Design,”IEICE Trans. on Electronics
, vol. E88-C , no. 6 , pp. 1322–1331 ,
Jun. 2005 (SCI,EI)
(34) Kuo-Hsing Cheng,Yu-Lung Lo, and Shu-Yu Jiang,“A Fast-Lock DLL with Power-On Reset Circuit,”IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
, vol. E87-A , pp. 2210-2220 ,
Sep. 2004 (SCI,EI)
(35) Kuo-Hsing Cheng, Wei-Bin Yang, and Chun-Fu Chung,“A Low-Power High-Driving Ability Voltage Control Oscillator used in PLL,”International J. of Electronics
, vol. 91 , pp. 361-375 ,
Jun. 2004 (EI,SCI)
(36) Kuo-Hsing Cheng, Wei-Bin Yang, and Cheng-Ming Ying,“A Dual-Slope Phase Frequency Detector and Charge Pump Architecture to Achieve Fast Locking of Phase-Locked Loop,”IEEE Trans. On Circuits and Systems Part II, Analog and Digital Signal Processing
, vol. 50 , pp. 892-896 ,
Nov. 2003 (EI,SCI)
(37) Kuo-Hsing Cheng and Wei-Bin Yang,“Circuit Analysis and Design of Low-Power CMOS Tapered Buffer,”IEICE Trans. Electron
, vol. E86-C , no. 5 , pp. 850-858 ,
May 2003 (EI,SCI)
(38) Kuo-Hsing Cheng and Wei-Bin Yang,“The Charge-Transfer Feedback-Controlled Split-Path CMOS Buffer,”IEEE Trans. On Circuits and Systems Part II, Analog and Digital Signal Processing
, vol. 46 , pp. 346-348 ,
Mar 1999 (EI,SCI)
(39) Kuo-Hsing Cheng and Huei-Chi Wang,“Design of Current Mode Operational Amplifier with Differential-Input and Differential-Output,”International J. of Electronics
, vol. 85 , pp. 443-453 ,
Oct. 1998 (EI,SCI)
(40) 黃弘一、鄭國興、吳重雨,“局部非同步邏輯電路的真單相時脈架構,”CCL Technical Journal
, pp. 63-70 ,
May 1995
(41) 鄭國興、吳重雨、王進賢,“無追撞四相動態邏輯CMOS的電路設計,”CCL Technical Journal
, pp. 40-48 ,
Apr. 1993
(42) Chung-Yu Wu, Kuo-Hsing Cheng and Jinn-Shyan Wang,“Analysis and Design of a New Race-Free Four-Phase CMOS Logic,”IEEE J. Solid State Circuits
, pp. 18-25 ,
Jan. 1993 (EI,SCI)
(43) Chung-Yu Wu and Kuo-Hsing Cheng,“Latched CMOS Differential Logic (LCDL) for Complex High-Speed VLSI,”IEEE J. Solid-State Circuits
, pp. 1325-1328 ,
Sep. 1991 (EI,SCI)
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International Conference Papers 共 107 篇
(1) Chih-Wei Tsai, Yu-Ting Chiu, Yo-Hao Tu, Kuo-Hsing Cheng, “A wide-range all-digital delay-locked loop for double data rate synchronous dynamic random access memory application,” in Proc. IEEE International Symposium on Circuits and Systems (ISCAS),
May. 2018, pp. 1-4
(2) Yo-Hao Tu, Kai-Wen Yao, Ming-Hao Huang, Yu-Yun Lin, Hao-Yu Chi, Po-Min Cheng, Pei-Yun Tsai, Muh-Tian Shiue, Chien-Nan Liu, Kuo-Hsing Cheng, and Jia-Shiang Fu, “A Body Sensor Node SoC for ECG/EMG Applications with Compressed Sensing and Wireless Powering,” in Proc. IEEE Int. Symp. on VLSI Design, Automation and Test,
Apr. 2017, pp. 1–4
(3) Yo-Hao Tu, Kuo-Hsing Cheng, Wei-Ren Wang, Jen-Chieh Liu, and Hong-Yi Huang, “A chaotically injected timing technique for ring-based oscillators,” in Proc. IEEE int. Symp. on Design and Diagnostics of Electronic Circuit & Syst.,
Apr. 2016, pp. 1-4
(4) Yo-Hao Tu, Kuo-Hsing Cheng, Yian-An Lin, and Hong-Yi Huang, “A Synchronous Mirror Delay with Duty-Cycle Tunable Technology,” in Proc. IEEE DDECS,
Apr. 2015, pp. 79-82
(5) Yo-Hao Tu, Kuo-Hsing Cheng, Chih-Hsun Hsu, and Hong-Yi Huang , “A low supply voltage synchronous mirror delay with quadrature phase output,” in Proc. IEEE DDECS,
Apr. 2014, pp. 163-166
(6) Yo-Hao Tu, Kuo-Hsing Cheng, Hsiang-Yun Wei, and Hong-Yi Huang, “A low jitter delay-locked-loop applied for DDR4,” in Proc. IEEE DDECS,
Apr. 2013, pp. 98-101
(7) Jen-Chieh Liu, Wei Chun Lee, Hong-Yi Huang, Kuo-Hsing Cheng, Chao-Jen Huang, Yu-Wei Liang, Jia-Hung Peng, and Yuan-Hua Chu, “A 0.3-V all digital crystal-less clock generator for energy harvester applications,” in Proc. IEEE ASSCC,
Nov. 2012, pp. 117-120
(8) Chih-Ping Cheng, Jen-Chieh Liu, and Kuo-Hsing Cheng , “Auto-calibration techniques in built-in jitter measurement circuit,” in Proc. IEEE DDECS,
Apr. 2012, pp. 248-249
(9) Bo-Qian Jiang, Cheng-Liang Hung, Bing-Hung Chen, and Kuo-Hsing Cheng, “A 6-Gb/s 3X-oversampling-like clock and data recovery in 0.13-µm CMOS technology,” in Proc. IEEE ISCAS,
Mar 2012, pp. 2597-2600
(10) Cheng-Liang Hung, Kuo-Hsing Cheng, Yu-Chen Lin, Bo-Qian Jiang, Che-Hao Fan, and Chi-Yang Chang, “A 0.06-psRMS SSC-induced jitter, ΔΣ-dithering-free, 6-GHz spread-spectrum clock generator for serial-ATA generation,” in Proc. ESSCIRC (ESSCIRC), 2011 Proceedings of the,
Sep. 2011
(11) Po-Chun Huang, Chi-Jih Shih, Yu-Chang Tsai,and Kuo-Hsing Cheng, “A phase error calibration DLL with edge combiner for wide-range operation ,” in Proc. New Circuits and Systems Conference (NEWCAS), 2011 IEEE 9th International,
Jun. 2011, pp. 1-4
(12) Tzu-Chi Huang, Hong-Yi Huang, Jen-Chieh Liu, Kuo-Hsing Cheng and Ching-Hsing Luo, “All digital phase-locked loop using active inductor oscillator and novel locking algorithm ,” in Proc. Circuits and Systems (ISCAS), 2011 IEEE International Symposium on,
May. 2011, pp. 486-489
(13) Kuo-Hsing Cheng, Chih-Yu Chang, Jen-Chieh Liu, Chih-Ping Cheng, “Measurement Error Analysis and Calibration Techniques for Built-in Jitter Measurement Circuit ,” in Proc. IEEE Trans. Very Large Scale Integr. Syst.,
Apr. 2011, pp. 1-4
(14) Meng-Fan Chang, Ku-Feng Lin, Che-Wei Wu, Yu-Sheng Chen, Pi-Feng Chiu, Chia-Chen Kuo, Yih-Shan Yang, Pei-Chia Chiang, Wen-Pin Lin, Che-He Lin, Heng-Yuan Lee, Pei-Yi Gu, Sum-Min Wang, Chen, F.T., Keng-Li Su, Chen-Hsin Lien, Kuo-Hsing Cheng, Hsin-Tun Wu, Tzu-Kun Ku, Ming-Jer Kao, and Ming-Jinn Tsai, “A 4Mb Embedded SLC Resistive-RAM Macro with 7.2ns Read-Write Random-Access Time and 160ns MLC-Access Capability,” in Proc. IEEE Int. Solid-State Circuits Conf. (ISSCC),
Feb. 2011, pp. 200-202
(15) Chi-Yang Chang, Cheng-Liang Hung, Yu-Chen Lin and Kuo-Hsing Cheng, “A 3 GHz spread-spectrum clock generator with a self-calibration technique ,” in Proc. New Circuits and Systems Conference (NEWCAS), 2011 IEEE 9th International ,
2011, pp. 177-180
(16) Yo-Hao Tu, Hsiang-Hao Chang, Cheng-Liang Hung, and Kuo-Hsing Cheng , “A 3 GHz DLL-Based Clock Generator with Stuck Locking Protection ,” in Proc. IEEE International Conference on Electronics, Circuits and Systems, ICECS,
Dec. 2010, pp. 106-109
(17) Yu-Chang Tsai, Kuo-Hsing Cheng, Yen-Hsueh Wu, and Ying-Fu Lin, “A CMOS Adaptive Equalizer Using Low-Voltage Zero Generators Technique,” in Proc. IEEE European Solid-State Circuits Conference,
Sep. 2010, pp. 546-549 (EI)
(18) Kai-Wei Hong, Kuo-Hsing Cheng, Chi-Hsiang Chen, Jen-Chieh Liu and Chien-Cheng Chen, “A Loading Effect Insensitive and High Precision Clock Synchronization Circuit,” in Proc. IEEE European Solid-State Circuits Conference,
Sep. 2010, pp. 514-517 (EI)
(19) Chia-Tsung Cheng, Yu-Chang Tsai, and Kuo-Hsing Cheng, “A High-Speed Current Mode Sense Amplifier for Spin-Torque Transfer Magnetic Random Access Memory,” in Proc. IEEE Midwest Symposium on Circuits and Systems,
Aug. 2010, pp. 181-184 (EI)
(20) Kuo-Hsing Cheng, Chang-Chien Hu, Jen-Chieh Liu, and Hong-Yi Huang, “A time-to-digital converter using multi-phase-sampling and time amplifier for all digital phase-locked loop,” in Proc. IEEE International Symposium on Design & Diagnostics of Electronic Circuits & Systems,
Apr. 2010, pp. 285-288
(21) Wei-Chang Liu; Chih-Hsien Lin; Shyh-Jye Jou; Hung-Wen Lu; Chau-Chin Su; Kai-Wei Hong; Kuo-Hsing Cheng; Shyue-Wen Yang; Ming-Hwa Sheu;, “A Micro-Network on Chip with 10-Gbs Transmission Link,” in Proc. ASSCC,
Nov. 2009, pp. 277 - 280
(22) Ting-Sheng Chao, Yu-Lung Lo, Wei-Bin Yang and Kuo-Hsing Cheng, “Designing Ultra-Low Voltage PLL Using a Bulk-Driven Technique,” in Proc. ESSCIRC,
Sep. 2009, pp. 388-391
(23) Shyh-shyuan Sheu,Pei-Chin Chiang,Wen-Pin Lin , Heng-Yuan Lee,Pang-Shiu Chen ,Yu-Sheng Chen,Frederick T.Chen ,Keng-Li Su ,Ming-Jer Kao, Kuo-Hsing Cheng, “A 5ns Fast Write Multi-Level Non-Volatile 1 K bits RRAM Memory with Advance Write Scheme,” in Proc. Symposium on VLSI Circuits Digest of Technical,
Jun. 2009, pp. 82-83
(24) Jen-Chieh Liu,Hong-Yi Huang,Wei-Bin Yang,Kuo-Hsing Cheng, “0.5v 160-MHz 260uW All Digital Phase-Locked Loop,” in Proc. The IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems,
Apr. 2009, pp. 186-193
(25) Kuo-Hsing Cheng, Chia-Wei Su, and Hsin-Hsin Ko, “A high-accuracy and high-efficiency on-chip current sensing for current-mode control CMOS DC-DC buck converter,” in Proc. IEEE International Conference on Electronics, Circuits and Systems, ICECS,
Aug. 2008, pp. 458-461 (EI)
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Patents
(1) 非石英時脈產生器及其運作方法, 台灣, 發明 第I520495號, 劉仁傑 張啟揚 涂祐豪 鄭國興 , 財團法人工業技術研究院 , 2016/02 至 2033/06
(2) Crystal-Less Clock Generator and Operation Method Thereof, 美國, 發明 第9024693號, 劉仁傑 張啟揚 涂祐豪 鄭國興 , 財團法人工業技術研究院, 2014/12 至 2028/12
(3) 電路最小分割和最小任意比例分割的方法, 台灣, 發明 第182649號, 鄭國興 鄭舜文 , 鄭國興 鄭舜文, 2003/07/11 至 2021/3/2
(4) 互補式金氧半電晶體(CMOS)動態邏輯架構, 台灣, 新型 第91732號, 鄭國興 吳重雨 , 行政院 國科會, 1994/07/01 至 2005/2/18
(5) 新型高速四相動態邏輯電路, 日本, 特許 第286678號, 鄭國興 吳重雨 , 行政院 國科會, 1998/12/18 至 2013/7/29
(6) CMOS Dynamic Logic Structure, 美國, 專利號碼：5,378,942, 鄭國興 吳重雨, 行政院 國科會, 1994/1/3 至 2011/1/3