Journal Conference Patents
Journal Papers 共 43 篇
(1) Jen-Chieh Liu, Yo-Hao Tu, Kuo-Hsing Cheng, and Chi-Yang Chang,“Low supply voltage and multiphase all-digital crystal-less clock generator,”IET Circuits, Devices & Syst.
, vol. 12 , no. 6 , pp. 720-725 ,
Aug. 2018 (SCI)
(2) Yo-Hao Tu, Kuo-Hsing Cheng, Man-Ju Lee, and Jen-Chieh Liu,“A power-saving adaptive equalizer with a digital-controlled self-slope detection,”IEEE Trans. Circuits Syst. I, Reg. Papers
, vol. 65 , no. 7 , pp. 2097–2108 ,
Jul. 2018 (EI,SCI)
(3) Yo-Hao Tu, Jen-Chieh Liu, Kuo-Hsing Cheng, and Chih-Hsun Hsu,“A 0.5-V all-digital clock-deskew buffer with I/Q phase outputs,”Analog Integrated Circuits and Signal Processing
, vol. 93 , no. 1 , pp. 157–167 ,
Oct. 2017 (SCI)
(4) Chih-Wei Tsai, Yu-Lung Lo, Chia-Chen Chang, Han-Ying Liu, Wei-Bin Yang, and Kuo-Hsing Cheng,“All-digital duty-cycle corrector with synchronous and high accuracy output for double date rate synchronous dynamic random-access memory application,”Japanese J. of Appl. Physics
, vol. 56 , no. 4S , pp. 04CF02-1 - 04CF02-6 ,
Jan. 2017
(5) Yo-Hao Tu, Jen-Chieh Liu, and Kuo-Hsing Cheng,“Proportional static-phase-error reduction for frequency-multiplier-based delay-locked-loop architecture,”IEICE Trans. on Electronics
, vol. E99-C , no. 6 , pp. 655-658 ,
Jan. 2016 (SCI)
(6) Yo-Hao Tu, Jen-Chieh Liu, Kuo-Hsing Cheng, Hong-Yi Huang, and Chang-Chien Hu,“A 0.6-V 1.6-GHz 8-phase all digital PLL using multi-phase based TDC,”IEICE Electronic Express
, vol. 13 , no. 2 , pp. 1-12 ,
Jan. 2016 (SCI)
(7) Kuo-Hsing Cheng, Cheng-Liang Hung, Alex Gong C.-S., Jen-Chieh Liu, Bo-Qian Jiang and Shi-Yang Sun,“A 0.9- to 8-GHz VCO with a differential active inductor for multistandard wireline SerDes,”IEEE Trans. Circuits Syst. II, Express Briefs
, vol. 61 , no. 8 , pp. 559-563 ,
Aug. 2014 (EI,SCI)
(8) Kuo-Hsing Cheng, Jen-Chieh Liu, and Hong-Yi Huang,“A 0.6-V 800-MHz All-Digital Phase-Locked Loop with a Digital Supply Regulator,”IEEE Trans. Circuits Syst. II, Express Briefs
, vol. 59 , no. 12 , pp. 888 - 892 ,
Dec. 2012 (EI,SCI)
(9) Kuo-Hsing Cheng, Kai-Wei Hong, Chi-Fa Hsu, and Bo-Qian Jiang ,“An All-Digital Clock Synchronization Buffer With One Cycle Dynamic Synchronizing,”IEEE Trans. Very Large Scale Integr. Syst.
, vol. 20 , no. 10 , pp. 1818-1827 ,
Oct. 2012 (EI,SCI)
(10) Shyh-Shyuan Sheu, Kuo-Hsing Cheng, Yu-Sheng Chen, Pang-Shiu Chen, Ming-Jinn Tsai, and Yu-Lung Lo,“A 50ns Verify Speed in Resistive random access memory by using a Write Resistance Tracking Circuit,”IEICE TRANSACTIONS ON ELECTRONICS
, vol. E95-C , no. 6 , pp. 1128-1131 ,
Jun. 2012 (SCI)
(11) Jen-Chieh Liu, Hong-Yi Huang, and Kuo-Hsing Cheng,“A 0.3 Volt All Digital Crystal-less Clock Generator,”ICL Technical Journal
, vol. 143 , no. 2 , pp. 126-133 ,
Feb. 2012
(12) Kuo-Hsing Cheng, Jen-Chieh Liu, and Hong-Yi Huang,“A 6-GHz Built-in Jitter Measurement Circuit Using Multiphase Sampler,”IEEE Trans. Circuits Syst. II, Express Briefs
, vol. 58 , no. 8 , pp. 492 ,
Aug. 2011 (EI,SCI)
(13) Kuo-Hsing Cheng, Kai-Wei Hong, Chi-Hsiang Chen, and Jen-Chieh Liu,“A High Precision Fast Locking Arbitrary Duty Cycle Clock Synchronization Circuit,”IEEE Trans. Very Large Scale Integr. Syst.
, vol. 19 , no. 7 , pp. 1218-1228 ,
Jul. 2011 (EI,SCI)
(14) Kuo-Hsing Cheng, Cheng-Liang Hung, and Chih-Hsien Chang,“A 0.77 ps RMS Jitter 6-GHz Spread-Spectrum Clock Generator Using a Compensated Phase-Rotating Technique,”IEEE J. Solid-State Circuits
, vol. 46 , no. 5 , pp. 1198-1213 ,
May 2011 (EI,SCI)
(15) Kuo-Hsing Cheng, Yu-Chang Tsai, Yu-Lung Lo, and Jing-Shiuan Huang,“A 0.5-V 0.4–2.24-GHz Inductorless Phase-Locked Loop in a System-on-Chip ,”IEEE Trans. Circuits Syst. I, Reg. Papers
, vol. 58 , no. 5 , pp. 849 ,
May 2011 (EI,SCI)
(16) Shyh-Shyuan Sheu and Kuo-Hsing Cheng,“Fast-Write Resistive RAM (RRAM) for Embedded Applications,”IEEE Design & Test of Computers
, vol. 28 , pp. 64-71 ,
Feb. 2011
(17) Kuo-Hsing Cheng, Kai-Wei Hong, Yu-Lung Lo, Chen-Lung Wu and Chien-Hsien Lee,“Dynamic frequency tracking and phase error compensation clock de-skew buffer,”IEE Electronics Letters
, vol. 46 , no. 25 , pp. 1653-1655 ,
Dec. 2010 (EI,SCI)
(18) Kuo-Hsing Cheng, Jen-Chieh Liu, Chih-Yu Chang, Shu-Yu Jiang, and Kai-Wei Hong,“Built-in Jitter Measurement Circuit with Calibration Techniques for a 3 GHz Clock Generator,”IEEE Trans. Very Large Scale Integr. Syst.
, pp. 1325-1335 ,
Jun. 2010 (EI,SCI)
(19) Kuo-Hsing Cheng, Yu-Chang Tsai, Yen-Hsueh Wu, and Ying-Fu Lin,“A 5Gb/s Inductorless CMOS Adaptive Equalizer for PCI Express Generation II Applications,”IEEE Trans. Circuits Syst. II, Express Briefs
, pp. 324-328 ,
May 2010 (EI,SCI)
(20) Kuo-Hsing Cheng, Shu-Yu Jiang, and Pei-Yi Jian,“A 2.5-GHz Built-in Jitter Measurement System in a Serial-Link Transceiver,”IEEE Trans. Very Large Scale Integr. Syst.
, vol. 17 , no. 12 , pp. 1698-1708 ,
Dec. 2009
(21) Yu-Lung Lo, Wei-Bin Yang, Ting-Sheng Chao, and Kuo-Hsing Cheng,“High-Speed and Ultra-Low-Voltage Divide-by-4/5 Counter for Frequency Synthesizer,”IEICE Trans. on Electronics
, pp. 0 ,
Jun. 2009 (EI,SCI)
(22) Yu-Lung Lo, Wei-Bin Yang, Ting-Sheng Chao, and Kuo-Hsing Cheng,“Designing an Ultra low-Voltage Phase-Locked Loop Using a Bulk-Driven Technique,”IEEE Trans. Circuits Syst. II, Express Briefs
, vol. 56 , no. 5 , pp. 339-343 ,
May 2009 (EI,SCI)
(23) Shu-Yu Jiang, Chan-Wei Huang, Yu-Lung Lo, and Kuo-Hsing Cheng,“Vernier Caliper and Equivalent-Signal Sampling for Built-in Jitter Measurement System,”IEICE Trans on Fundamentals of Electronics, Communications and Computer Sciences
, pp. 389-400 ,
Jan. 2009 (EI,SCI)
(24) Kuo-Hsing Cheng, Yu-Chang Tsai, Chien-Han Jimmy Liu, Kai-Wei Hong, and Chin-Cheng Kuo,“A low jitter self-calibration PLL for 10-Gbps SoC transmission lines application,”IEICE Trans. Electron
,
Jan. 2009
(25) Kuo-Hsing Cheng, Chia-Wei Su, and Hsin-Hsin Ko,“Highly Accurate and Efficient Current-Mode PWM CMOS DC-DC Buck Converter with On-Chip Current-Sensing,”IEICE Trans. on Electronics
, pp. 1941-1950 ,
Dec. 2008 (EI)
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International Conference Papers 共 107 篇
(1) Chih-Wei Tsai, Yu-Ting Chiu, Yo-Hao Tu, Kuo-Hsing Cheng, “A wide-range all-digital delay-locked loop for double data rate synchronous dynamic random access memory application,” in Proc. IEEE International Symposium on Circuits and Systems (ISCAS),
May. 2018, pp. 1-4
(2) Yo-Hao Tu, Kai-Wen Yao, Ming-Hao Huang, Yu-Yun Lin, Hao-Yu Chi, Po-Min Cheng, Pei-Yun Tsai, Muh-Tian Shiue, Chien-Nan Liu, Kuo-Hsing Cheng, and Jia-Shiang Fu, “A Body Sensor Node SoC for ECG/EMG Applications with Compressed Sensing and Wireless Powering,” in Proc. IEEE Int. Symp. on VLSI Design, Automation and Test,
Apr. 2017, pp. 1–4
(3) Yo-Hao Tu, Kuo-Hsing Cheng, Wei-Ren Wang, Jen-Chieh Liu, and Hong-Yi Huang, “A chaotically injected timing technique for ring-based oscillators,” in Proc. IEEE int. Symp. on Design and Diagnostics of Electronic Circuit & Syst.,
Apr. 2016, pp. 1-4
(4) Yo-Hao Tu, Kuo-Hsing Cheng, Yian-An Lin, and Hong-Yi Huang, “A Synchronous Mirror Delay with Duty-Cycle Tunable Technology,” in Proc. IEEE DDECS,
Apr. 2015, pp. 79-82
(5) Yo-Hao Tu, Kuo-Hsing Cheng, Chih-Hsun Hsu, and Hong-Yi Huang , “A low supply voltage synchronous mirror delay with quadrature phase output,” in Proc. IEEE DDECS,
Apr. 2014, pp. 163-166
(6) Yo-Hao Tu, Kuo-Hsing Cheng, Hsiang-Yun Wei, and Hong-Yi Huang, “A low jitter delay-locked-loop applied for DDR4,” in Proc. IEEE DDECS,
Apr. 2013, pp. 98-101
(7) Jen-Chieh Liu, Wei Chun Lee, Hong-Yi Huang, Kuo-Hsing Cheng, Chao-Jen Huang, Yu-Wei Liang, Jia-Hung Peng, and Yuan-Hua Chu, “A 0.3-V all digital crystal-less clock generator for energy harvester applications,” in Proc. IEEE ASSCC,
Nov. 2012, pp. 117-120
(8) Chih-Ping Cheng, Jen-Chieh Liu, and Kuo-Hsing Cheng , “Auto-calibration techniques in built-in jitter measurement circuit,” in Proc. IEEE DDECS,
Apr. 2012, pp. 248-249
(9) Bo-Qian Jiang, Cheng-Liang Hung, Bing-Hung Chen, and Kuo-Hsing Cheng, “A 6-Gb/s 3X-oversampling-like clock and data recovery in 0.13-µm CMOS technology,” in Proc. IEEE ISCAS,
Mar 2012, pp. 2597-2600
(10) Cheng-Liang Hung, Kuo-Hsing Cheng, Yu-Chen Lin, Bo-Qian Jiang, Che-Hao Fan, and Chi-Yang Chang, “A 0.06-psRMS SSC-induced jitter, ΔΣ-dithering-free, 6-GHz spread-spectrum clock generator for serial-ATA generation,” in Proc. ESSCIRC (ESSCIRC), 2011 Proceedings of the,
Sep. 2011
(11) Po-Chun Huang, Chi-Jih Shih, Yu-Chang Tsai,and Kuo-Hsing Cheng, “A phase error calibration DLL with edge combiner for wide-range operation ,” in Proc. New Circuits and Systems Conference (NEWCAS), 2011 IEEE 9th International,
Jun. 2011, pp. 1-4
(12) Tzu-Chi Huang, Hong-Yi Huang, Jen-Chieh Liu, Kuo-Hsing Cheng and Ching-Hsing Luo, “All digital phase-locked loop using active inductor oscillator and novel locking algorithm ,” in Proc. Circuits and Systems (ISCAS), 2011 IEEE International Symposium on,
May. 2011, pp. 486-489
(13) Kuo-Hsing Cheng, Chih-Yu Chang, Jen-Chieh Liu, Chih-Ping Cheng, “Measurement Error Analysis and Calibration Techniques for Built-in Jitter Measurement Circuit ,” in Proc. IEEE Trans. Very Large Scale Integr. Syst.,
Apr. 2011, pp. 1-4
(14) Meng-Fan Chang, Ku-Feng Lin, Che-Wei Wu, Yu-Sheng Chen, Pi-Feng Chiu, Chia-Chen Kuo, Yih-Shan Yang, Pei-Chia Chiang, Wen-Pin Lin, Che-He Lin, Heng-Yuan Lee, Pei-Yi Gu, Sum-Min Wang, Chen, F.T., Keng-Li Su, Chen-Hsin Lien, Kuo-Hsing Cheng, Hsin-Tun Wu, Tzu-Kun Ku, Ming-Jer Kao, and Ming-Jinn Tsai, “A 4Mb Embedded SLC Resistive-RAM Macro with 7.2ns Read-Write Random-Access Time and 160ns MLC-Access Capability,” in Proc. IEEE Int. Solid-State Circuits Conf. (ISSCC),
Feb. 2011, pp. 200-202
(15) Chi-Yang Chang, Cheng-Liang Hung, Yu-Chen Lin and Kuo-Hsing Cheng, “A 3 GHz spread-spectrum clock generator with a self-calibration technique ,” in Proc. New Circuits and Systems Conference (NEWCAS), 2011 IEEE 9th International ,
2011, pp. 177-180
(16) Yo-Hao Tu, Hsiang-Hao Chang, Cheng-Liang Hung, and Kuo-Hsing Cheng , “A 3 GHz DLL-Based Clock Generator with Stuck Locking Protection ,” in Proc. IEEE International Conference on Electronics, Circuits and Systems, ICECS,
Dec. 2010, pp. 106-109
(17) Yu-Chang Tsai, Kuo-Hsing Cheng, Yen-Hsueh Wu, and Ying-Fu Lin, “A CMOS Adaptive Equalizer Using Low-Voltage Zero Generators Technique,” in Proc. IEEE European Solid-State Circuits Conference,
Sep. 2010, pp. 546-549 (EI)
(18) Kai-Wei Hong, Kuo-Hsing Cheng, Chi-Hsiang Chen, Jen-Chieh Liu and Chien-Cheng Chen, “A Loading Effect Insensitive and High Precision Clock Synchronization Circuit,” in Proc. IEEE European Solid-State Circuits Conference,
Sep. 2010, pp. 514-517 (EI)
(19) Chia-Tsung Cheng, Yu-Chang Tsai, and Kuo-Hsing Cheng, “A High-Speed Current Mode Sense Amplifier for Spin-Torque Transfer Magnetic Random Access Memory,” in Proc. IEEE Midwest Symposium on Circuits and Systems,
Aug. 2010, pp. 181-184 (EI)
(20) Kuo-Hsing Cheng, Chang-Chien Hu, Jen-Chieh Liu, and Hong-Yi Huang, “A time-to-digital converter using multi-phase-sampling and time amplifier for all digital phase-locked loop,” in Proc. IEEE International Symposium on Design & Diagnostics of Electronic Circuits & Systems,
Apr. 2010, pp. 285-288
(21) Wei-Chang Liu; Chih-Hsien Lin; Shyh-Jye Jou; Hung-Wen Lu; Chau-Chin Su; Kai-Wei Hong; Kuo-Hsing Cheng; Shyue-Wen Yang; Ming-Hwa Sheu;, “A Micro-Network on Chip with 10-Gbs Transmission Link,” in Proc. ASSCC,
Nov. 2009, pp. 277 - 280
(22) Ting-Sheng Chao, Yu-Lung Lo, Wei-Bin Yang and Kuo-Hsing Cheng, “Designing Ultra-Low Voltage PLL Using a Bulk-Driven Technique,” in Proc. ESSCIRC,
Sep. 2009, pp. 388-391
(23) Shyh-shyuan Sheu,Pei-Chin Chiang,Wen-Pin Lin , Heng-Yuan Lee,Pang-Shiu Chen ,Yu-Sheng Chen,Frederick T.Chen ,Keng-Li Su ,Ming-Jer Kao, Kuo-Hsing Cheng, “A 5ns Fast Write Multi-Level Non-Volatile 1 K bits RRAM Memory with Advance Write Scheme,” in Proc. Symposium on VLSI Circuits Digest of Technical,
Jun. 2009, pp. 82-83
(24) Jen-Chieh Liu,Hong-Yi Huang,Wei-Bin Yang,Kuo-Hsing Cheng, “0.5v 160-MHz 260uW All Digital Phase-Locked Loop,” in Proc. The IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems,
Apr. 2009, pp. 186-193
(25) Kuo-Hsing Cheng, Chia-Wei Su, and Hsin-Hsin Ko, “A high-accuracy and high-efficiency on-chip current sensing for current-mode control CMOS DC-DC buck converter,” in Proc. IEEE International Conference on Electronics, Circuits and Systems, ICECS,
Aug. 2008, pp. 458-461 (EI)
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Patents
(1) 非石英時脈產生器及其運作方法, 台灣, 發明 第I520495號, 劉仁傑 張啟揚 涂祐豪 鄭國興 , 財團法人工業技術研究院 , 2016/02 至 2033/06
(2) Crystal-Less Clock Generator and Operation Method Thereof, 美國, 發明 第9024693號, 劉仁傑 張啟揚 涂祐豪 鄭國興 , 財團法人工業技術研究院, 2014/12 至 2028/12
(3) 電路最小分割和最小任意比例分割的方法, 台灣, 發明 第182649號, 鄭國興 鄭舜文 , 鄭國興 鄭舜文, 2003/07/11 至 2021/3/2
(4) 互補式金氧半電晶體(CMOS)動態邏輯架構, 台灣, 新型 第91732號, 鄭國興 吳重雨 , 行政院 國科會, 1994/07/01 至 2005/2/18
(5) 新型高速四相動態邏輯電路, 日本, 特許 第286678號, 鄭國興 吳重雨 , 行政院 國科會, 1998/12/18 至 2013/7/29
(6) CMOS Dynamic Logic Structure, 美國, 專利號碼：5,378,942, 鄭國興 吳重雨, 行政院 國科會, 1994/1/3 至 2011/1/3